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標(biāo)題: RS232狀態(tài)機Verilog編程問題... [打印本頁]

作者: eqgyzgs 時間: 2012-7-16 16:51
標(biāo)題: RS232狀態(tài)機Verilog編程問題...
編譯的時候出現(xiàn)
Error: Node "CLK" of type Register cell has no legal location
Error: Can't fit design in device
這兩個錯誤...我用的開發(fā)板芯片是EP2C8Q208C...產(chǎn)生這兩個錯誤的原因是什么？是開發(fā)平臺的設(shè)置問題還是我的代碼問題？
以下是完整代碼

module Test(CLK_50M,REST,DAT,RXEXT,RXD,TXLD,TXD,READY);//READY=11:RX and TX is idle;READY=0x:RX is busy and TX is idle;READY=x0:RX is idle and TX is busy;
input CLK_50M,REST;
inout [7:0] DAT;
input RXEXT,RXD;
input TXLD;
output TXD;
output [1:0] READY;
reg TXD;
reg [7:0] DAT;
reg [1:0] READY;
reg [15:0] CNT;
reg CLK;
reg [2:0] CLKSTATE;
reg [7:0] RXBUFF,TXBUFF;
reg RXBUFF1,RXBUFF2;//異步通信，接收使用兩級緩存
reg RXEN,TXEN;
reg [3:0] RXSTATE,TXSTATE;
parameter Start=4'b0000,
Bit0=4'b0001,Bit1=4'b0010,Bit2=4'b0011,Bit3=4'b0100,Bit4=4'b0101,Bit5=4'b0110,Bit6=4'b0111,Bit7=4'b1000,
Stop=4'b1001,
BaudRate8x=16'd324;//9600
always @(posedge CLK_50M or negedge REST)//分頻
if(!REST) CNT <= 16'h0000;
else if(CNT!=BaudRate8x) CNT <= CNT+1'b1;
else CNT <= 16'h0000;

always @(posedge CLK_50M or negedge REST)
if(!REST) CLK <= 1'b0;
else if(CNT==BaudRate8x) CLK <= ~CLK;

always @(posedge CLK or negedge REST)//記錄時隙
if(!REST) CLKSTATE <= 3'b000;
else CLKSTATE <= CLKSTATE+1'b1;

always @(CLKSTATE)//發(fā)送使能
if(CLKSTATE==3'b111) TXEN=1;
else TXEN=0;

always @(CLKSTATE)//接收使能
if(CLKSTATE==3'b111) RXEN=1;
else RXEN=0;

always @(posedge CLK)//發(fā)送緩沖
if((READY==2'bx1)&&TXLD) TXBUFF <= DAT;

always @(posedge CLK)//接收提取
if((READY==2'b1x)&&RXEXT) DAT <= RXBUFF;

always @(posedge CLK or negedge REST)//發(fā)送
if(!REST)begin TXBUFF <= 8'h00;TXSTATE <= 4'h0; end
else if(TXBUFF)
 case(TXSTATE)
Start:if(TXEN)begin TXD <= 1'b0;TXSTATE <= Bit0;READY[0] <= 1'b0; end
Bit0:if(TXEN)begin TXD <= TXBUFF[0];TXSTATE <= Bit1; end
Bit1:if(TXEN)begin TXD <= TXBUFF[1];TXSTATE <= Bit2; end
Bit2:if(TXEN)begin TXD <= TXBUFF[2];TXSTATE <= Bit3; end
Bit3:if(TXEN)begin TXD <= TXBUFF[3];TXSTATE <= Bit4; end
Bit4:if(TXEN)begin TXD <= TXBUFF[4];TXSTATE <= Bit5; end
Bit5:if(TXEN)begin TXD <= TXBUFF[5];TXSTATE <= Bit6; end
Bit6:if(TXEN)begin TXD <= TXBUFF[6];TXSTATE <= Bit7; end
Bit7:if(TXEN)begin TXD <= TXBUFF[7];TXSTATE <= Stop; end
Stop:if(TXEN)begin TXD <= 1'b1;TXSTATE <= 4'b0000;READY[0] <= 1'b1; end
default:begin TXSTATE <= 4'b0000;TXBUFF <= 8'h00;READY[0] <= 1'b1; end
 endcase

always @(posedge CLK or negedge REST)//接收
if(!REST)begin RXBUFF <= 8'h00;RXSTATE <= 4'h0; end
else begin
 RXBUFF1 <= RXD;
 RXBUFF2 <= RXBUFF1;
 case(RXSTATE)
Start:if(!RXD)begin RXSTATE <= Bit0;READY[1] <= 1'b0; end
 else begin RXSTATE <= 4'b0000;READY[1] <= 1'b1; end
Bit0:if(RXEN)begin RXBUFF[0] <= RXBUFF2;RXSTATE <= Bit1; end
Bit1:if(RXEN)begin RXBUFF[1] <= RXBUFF2;RXSTATE <= Bit2; end
Bit2:if(RXEN)begin RXBUFF[2] <= RXBUFF2;RXSTATE <= Bit3; end
Bit3:if(RXEN)begin RXBUFF[3] <= RXBUFF2;RXSTATE <= Bit4; end
Bit4:if(RXEN)begin RXBUFF[4] <= RXBUFF2;RXSTATE <= Bit5; end
Bit5:if(RXEN)begin RXBUFF[5] <= RXBUFF2;RXSTATE <= Bit6; end
Bit6:if(RXEN)begin RXBUFF[6] <= RXBUFF2;RXSTATE <= Bit7; end
Bit7:if(RXEN)begin RXBUFF[7] <= RXBUFF2;RXSTATE <= Stop; end
Stop:if(RXEN&&RXD)begin RXSTATE <= 4'b0000;READY[1] <= 1'b1; end
 else begin RXSTATE <= Bit0;READY[1] <= 1'b0; end
default:begin RXSTATE <= 4'b0000;RXBUFF <= 8'h00;READY[1] <= 1'b1; end
 endcase
end
endmodule

作者: asyou 時間: 2012-7-16 16:51
時鐘要放到時鐘引腳上！

作者: zhping12 時間: 2012-7-17 14:08
時鐘信號一定要配置在相對應(yīng)的管腳上，否則編譯過不了。

作者: eqgyzgs 時間: 2012-7-17 16:40
回復(fù)2樓asyou：
貌似還真是這樣子...新建一個工程不分配引腳就能通過編譯了...受教了~

作者: 3637320230 時間: 2012-12-2 08:50

歡迎光臨電子工程網(wǎng) (http://m.4huy16.com/)

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